A Phone-Size Superchip? Intel Thinks So

Intel Foundry's extreme multi-chiplet architecture integrates 16 compute tiles and 24 HBM5 stacks in a single US-made package

13 Mar 2026

Intel has unveiled a semiconductor packaging architecture designed to push the physical limits of conventional chip manufacturing, combining multiple computing and memory components within a single large package.

The design, disclosed by Intel Foundry in December 2025, integrates 16 compute tiles and 24 stacks of next-generation high-bandwidth memory, or HBM5. The overall package extends to more than 12 times the size of a standard lithography reticle, the area that can normally be patterned on a chip in a single step.

Rather than relying on a single large silicon die, the architecture uses a disaggregated approach in which specialised chiplets are stacked and connected using advanced packaging technologies.

Compute tiles are bonded vertically using Intel’s Foveros Direct 3D method, which employs copper-to-copper hybrid bonding with connection pitches below 10 microns. The chiplets are also linked laterally using EMIB-T, an updated version of Intel’s embedded multi-die interconnect bridge that incorporates through-silicon vias to improve data transfer across the package.

The resulting system spans roughly the dimensions of a smartphone but is designed to function as a unified computing platform.

Intel said the architecture is intended for data-intensive workloads such as artificial intelligence training and scientific computing. As AI hardware clusters approach power levels of about 100 kilowatts per rack, engineers have sought to position high-bandwidth memory close to processing logic to reduce latency and improve data throughput.

The proposed design can support up to 24 HBM5 stacks alongside 48 LPDDR5x memory controllers, providing the memory bandwidth required by large AI models and simulation workloads.

A smaller version of the architecture, combining four compute tiles with 12 memory stacks, could be manufactured using current production techniques. The full configuration is expected to depend on the maturity of Intel’s planned 14A process node, with commercial deployment targeted later in the decade.

Engineers still face challenges around manufacturing yield, thermal management and power delivery at this scale.

Intel is positioning the technology as a competitor to Taiwan Semiconductor Manufacturing Company’s CoWoS-L advanced packaging platform, which supports packages up to roughly 9.5 times reticle size. The company said the system would also form part of its foundry offering for external customers seeking advanced semiconductor manufacturing capacity in the US.