Highlights of the Program

2 days business program:

Learn from real-world case studies by industry leaders.

SHOWCASING INNOVATION:

Discover the latest technology and techniques from across the industry.

leaders talk:

Hear from top-level experts about how to stay ahead in a fast-changing industry.

MULTIPLE STREAMS:

A business program that is multi-disciplinary, giving you a broad view of the industry.

SMART TECHNOLOGIES:

Explore the latest smart and AI-driven solutions, and see how they can be used in your business.

roundtable discussion:

Join talks with industry peers. Share ideas, make connections, and find new partners.

Program

Day 1 :

MONDAY, JUNE 8, 2026

08:30 - 09:30

REGISTRATION AND MORNING REFRESHMENTS

09:30 - 09:40

OPENING ADDRESS

09:40 - 10:05

CHIPLETS FOR EVERYONE IN THE ERA OF PHYSICAL AI

Mick Posner

Cadence

Explaining the shift from monolithic SoCs to modular chiplets addressing cost and scaling limits
Highlighting chiplet benefits for edge and Physical AI needing power efficient real time compute
Examining standardization and ecosystems enabling interoperable plug and play chiplets at scale

10:05 - 10:10

Q&A SESSION ON INTEROPERABLE CHIPLETS FOR PHYSICAL AI

10:10 - 10:40

SPEED NETWORKING SESSION

Exchange business cards and get connected in short one-to-one meetings
Start the conversation to arrange a more formal meeting later on in the conference
Share your professional background and discuss your biggest business issues ̶ don't forget your business cards!

10:40 - 11:00

MORNING COFFEE BREAK IN THE EXHIBIT AREA

11:00 - 11:30

PANEL DISCUSSION ON CHIPLETS

11:30 - 11:55

PATH-AI FOR ARCHITECTURE OPTIMIZATION IN CHIPLET-BASED AI SYSTEMS

Vidya Chhabria

Arizona State University

Modeling coupled workload mapping, chiplet composition, and packaging impacts on AI systems
Formulating latency, energy, area, and cost models with explicit die-to-die communication effects
Optimizing architectures using simulated annealing and caching for early-stage pathfinding

11:55 - 12:00

Q&A SESSION ON PATHFINDING FOR HETEROGENEOUS CHIPLET AI

12:00 - 13:30

NETWORKING LUNCH & VISITING THE CHIPLET EXHIBITION

13:30 - 13:55

A UNIFIED DATA LAKE PLATFORM FOR ACCELERATING R&D INNOVATION

Ananth Kommuri

Amazon Web Services

Integrating multi source manufacturing data via GEM OPC-UA and MQTT into a scalable AI ready lake
Applying AI and ML to yield optimization anomaly detection root cause analysis and maintenance
Demonstrating quantified gains including faster R&D cycles improved yield learning and uptime

13:55 - 14:00

Q&A SESSION ON AI DATA PLATFORMS FOR SEMICONDUCTOR R&D

14:00 - 14:25

DESIGN-FOR-TEST MAKES OR BREAKS MULTI-DIE PRODUCTS

Martin Keim

Siemens

Emphasizing DFT as mandatory at multi-die product inception to avoid irreversible cost risks
Warning that undersized or late DFT decisions will directly jeopardize yield and viability
Illustrating how robust DFT enables visibility from die test to field use and life extension

14:25 - 14:30

Q&A SESSION ON DFT STRATEGIES FOR MULTI-DIE SUCCESS

14:30 - 15:00

AFTERNOON COFFEE BREAK IN THE EXHIBIT AREA

15:00 - 15:25

MISSION-CRITICAL CHIPLET ARCHITECTURES FOR RESILIENT EDGE AI

Tayo Adesanya

Lola Vision Systems

Architecting heterogeneous AI chiplet systems for low SWaP autonomy in mission platforms
Enabling 2.5D integration thermal aware packaging and secure fabrics for reliable edge comput
Showcasing a case study on resilient sensing RF coexistence and real time tactical decisions

15:25 - 15:30

Q&A SESSION ON RESILIENT EDGE AI CHIPLET ARCHITECTURES

15:30 - 15:55

HIGH-TEMPERATURE SUPERCONDUCTORS FOR HPC AI AND QUANTUM SENSORS

Liam Kelly

Ambature

Surveying superconducting material systems' operating ranges and performance tradeoffs
Quantifying computing and sensing gains, including speed, energy efficiency, and interconnects
Identifying integration and packaging opportunities requiring further research and validation

15:55 - 16:00

Q&A SESSION ON SUPERCONDUCTORS IN ADVANCED COMPUTING SYSTEMS

16:00 - 17:00

NETWORKING DRINKS RECEPTION

Day 2 :

TUESDAY, JUNE 9, 2026

09:00 - 09:30

MORNING REFRESHMENTS

09:30 - 09:40

OPENING ADDRESS

09:40 - 10:05

DESIGNING AI-READY DATA CENTERS FOR RISING CHIP POWER DENSITY

Rishab Vardhan

Oracle

Analyzing how chiplet and AI accelerator power density shifts drive extreme rack heat loads
Assessing impacts on data center architecture, including cooling, flow, power delivery, and space
Detailing liquid cooling deployments, lessons, constraints, and strategies for future high TDP chips

10:05 - 10:10

Q&A SESSION ON DATA CENTER DESIGN FOR HIGH POWER AI CHIPS

10:10 - 10:35

CONTACTLESS LASER DEPOSITION FOR HIGH RESOLUTION CONDUCTIVE MATERIALS

Stephane Etienne

ioTech

Advancing sustainable plating alternatives by avoiding acids and water while cutting material waste
Introducing CLAD as a digital additive method replacing imaging based plating with selective drops
Explaining film coated materials released by laser bursts into consistent droplets onto substrates
Enabling inline curing or sintering plus fine resolution geometries for solder paste deposition at speed

10:35 - 10:40

Q&A SESSION ON LASER ASSISTED ADDITIVE DEPOSITION FOR PACKAGING

10:40 - 11:00

MORNING COFFEE BREAK IN THE EXHIBIT AREA

11:00 - 11:25

SCALING VACUUM GETTER PROCESSES FOR ADVANCED SUBSTRATES

Veit Große

Kurtz Ersa

Explaining component-specific design demands and integration constraints in vacuum getter systems
Detailing high-vacuum getter activation workflows and critical controls for hermetic sealing
Demonstrating thermal isolation enabling 450°C sealing while protecting devices below 100°C

11:25 - 11:30

Q&A SESSION ON VACUUM GETTER THERMAL CONTROL STRATEGIES

11:30 - 12:00

RESERVED PRESENTATION

12:00 - 12:15

FEEDBACK AND RAFFLE DRAW

12:15 - 13:30

NETWORKING LUNCH

Become a Speaker & Join the Conversation

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