Chip Design Just Got 10× Faster With AI

Al speeds Samsung-Synopsys chip design by 10x, with sharper signal integrity and certified efficiency gains.

19 Jun 2025

Chip design is usually slow. Manual routing and signal checks stretch timelines and inflate costs. But in June Samsung and Synopsys claimed a tenfold speed-up in developing a high-bandwidth-memory (HBM3) multi-die chip on Samsung's 2-nanometre process. Routing fell to four hours, while signal quality improved by 6%. Certified Al flows also showed gains in performance, power and area, hinting that automation is reshaping semiconductor design.

Chiplets, modular dies that can be assembled into larger processors, are central to this shift. They promise efficiency but have long required painstaking manual work. Synopsys' Al-driven design tools, including its 3DIC Compiler for planning and routing, cut through these bottlenecks. The result is faster iteration and less uncertainty.

The 6% improvement in signal integrity looks small, but for memory-heavy designs like HBM3 it matters. Even incremental gains scale up to big efficiency savings in data centres, supercomputers and Al accelerators. Faster turnaround also means firms can test more ideas and reach the market sooner.

There are caveats. Engineers still question how Al makes its choices, and applying these methods across different chipmaking processes will not be simple. Yet the Samsung and Synopsys results suggest the tools are practical, and adoption is likely to grow.

By improving both speed and quality, Al may be starting to chip away at long-standing barriers in multi-die design, an industry where every hour and every percentage point counts.